Education kit for teaching computer architecture with a 5-stage Arm-based Verilog core and hands-on labs (educational)

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

🔎 Detect architectures, platforms, shells, terminals, CI systems and agents, grouped by family

Formalizing the Intel 4004 microprocessor

This repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) of the Cell Broadband Engine architecture.

VHDL , ModelSIM, Quartus, FPGA, Image Processing

Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).

An analysis of intels goldmont plus uarch predecode caches core logic due to it being undocumented

The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture.

5 Stage Pipelined RV32I SoC with Hardware Enforced CFI, Dual Port Synchronous Memory Controller and Bidirectional UART implemented in VHDL

Μια ενδεικτική υλοποίηση RISC-V επεξεργαστή και ενός υποστηρικτικού Assembler - Διπλωματική εργασία στο Τμήμα Μηχανικών Η/Υ και Πληροφορικής, Πανεπιστήμιο Πατρών / An Indicative RISC-V CPU Implementation and an Accompanying Assembler - Master's Diploma Thesis at the Computer Engineering and Informatics Department (CEID), University of Patras

Assembler, ISA & everything else featuring the 16-Bit Minecraft Redstone CPU "Frostybte"

A Verilog project for designing an Arithmetic Logic Unit (ALU) using pre-existing logic blocks. This ALU performs fundamental operations such as addition, subtraction, and logical shifts in a CPU architecture.

[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.

A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)

Code snippets for the CpuFun blog

custom CPU emulator and assembler

[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor

A single-cycle RISC-V CPU implementation in Logisim