Opentitan earlgrey changes for upstream by lexbaileylowrisc · Pull Request #323 · lowRISC/qemu

lexbaileylowrisc · 2026-02-19T11:02:36Z

DO NOT MERGE
this is just so we know what we're proposing upstream

This is the start of efforts to contribute code from the lowRISC fork of QEMU to bring the QEMU support for OpenTitan machines in line with Earl Grey 1.0 by adding a new machine called ot-earlgrey. This work was done by Emmanuel Blot and Loïc Lefort from Rivos, and various people at lowRISC. This patch set in particular adds the basic machine definition, and one of the peripherals required for it: the alert handler device. I previously emailed asking for advice on how to test our changes in a way that is acceptable upstream, and how best to submit such a large set of changes, if anyone has more thoughts on that, please do reply to that email. (https://lists.nongnu.org/archive/html/qemu-riscv/2026-02/msg00139.html) There's lots more commits to come, I don't want to dump too much on the mailing list all at once. For now this is a small first step. This patch set should give a flavour of the style of what's to come, and I'm expecting there will be some changes required. We'd just like to understand what will be needed to make this acceptable as soon as we can before we try to upstream lots more of these changes. In particular, most of our new peripheral blocks are currently in the directory called hw/opentitan. In our fork we have about 60 blocks in this directory, we have put them there to keep them organised as opentitan-specific blocks. Is this a suitable place for them? would you prefer a different structure? Thanks! To: qemu-devel@nongnu.org Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Alistair Francis <alistair.francis@wdc.com> Cc: Weiwei Li <liwei1518@gmail.com> Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> Cc: qemu-riscv@nongnu.org Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Cc: Alistair Francis <alistair@alistair23.me> Cc: Pierrick Bouvier <pierrick.bouvier@linaro.org> Cc: Dr. David Alan Gilbert <dave@treblig.org> Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: lowRISC <qemu-maintainers@lowrisc.org> Cc: nabihestefan@google.com <nabihestefan@google.com> Cc: Amit Kumar-Hermosillo <amitkh@google.com> Signed-off-by: Lex Bailey <lex.bailey@lowrisc.org> --- b4-submit-tracking --- # This section is used internally by b4 prep for tracking purposes. { "series": { "revision": 1, "change-id": "20260217-opentitan-earlgrey-474a14215feb", "prefixes": [ "RFC" ] } }

Follow vendor-device syntax used with other RISCV cores Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

Use a separate Kconfig symbols for Ibex UART, Timer, and SPI devices: having an Ibex CPU does not imply usage of these specific implementations. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

jwnrt · 2026-02-19T13:39:07Z

hw/opentitan/meson.build

+# TomCrypt dependency
+
+libtomcrypt_dep = subproject('libtomcrypt').get_variable('libtomcrypt_dep')
+


I don't think we're submitting libtomcrypt

yep, missed this, removed

jwnrt · 2026-02-19T13:40:47Z

hw/opentitan/ot_alert.c

+ * Note: for now, only a minimalist subset of Power Manager device is
+ *       implemented in order to enable OpenTitan's ROM boot to progress


Is this still true in this submission?

I think this comment is a copy-paste error anyway. removed.

AlexJones0

I've left a few comments.

One additional general comment I have is that I wonder if it is also easier just to recreate the OpenTitan machine from scratch (like we are with the alert handler peripheral here), rather than pulling commits from the history.

Otherwise, there might be a lot of review noise as we add later commits to e.g. change PLIC and alert mapping numbers (iirc, this happens a lot). It is also a bit strange from the perspective of upstream to introduce an OT Earlgrey machine based on RTL from an old commit and then continually update it over time.

At the same time, that would then also require effort to recreate the Earlgrey machine in new commits as well. But the benefit is that we would give up on rebasing and we then don't have to go through the process of getting all those intermediary change commits reviewed. I suspect this would become a problem anyway, because if review comments require us to change a lot of stuff, then the rebases would become even more painful anyway.

WDYT @lexbaileylowrisc @jwnrt @luismarques?

AlexJones0 · 2026-02-19T12:50:21Z

target/riscv/monitor.c


    mem_info_svxx(mon, env);
 }
+


Do we need this commit for this patch? (adding general RISC-V registers to the monitor). It seems like a convenience commit to me, and directly contradicts the existing comment in the code.

Even if we did want it, I suspect it would be better as a separate patch/contribution.

AlexJones0 · 2026-02-19T12:51:26Z

include/hw/ssi/ssi.h


 typedef enum SSICSMode SSICSMode;

+#define TYPE_SSI_BUS "SSI"


I suspect upstream will want us to motivate this change - it would be good to try and figure out why we need the SSI bus to be public (where are we using it, and why? Why is this the correct solution?)

turns out it's not needed. removed.

AlexJones0 · 2026-02-19T12:56:08Z

docs/opentitan/index.md

@@ -0,0 +1,25 @@
+# Ibex SoC emulation


A few thoughts:

I suspect upstream will desire .rst files, not .md files.

I suspect docs/opentitan/ is too non-specific, it is likely we will want docs to live somewhere like system/devices/opentitan/ and / or system/riscv/opentitan/ depending on what is being documented.

Maybe it's fine to leave it as is, but I wonder if upstream won't want us replicating QEMU build command docs here? Just a thought.

I think I will leave this like this for now (for the sake of speed) if upstream complains then we'll change it

AlexJones0 · 2026-02-19T13:07:09Z

target/riscv/cpu.h

    uint64_t henvcfg;
+
+    /* Ibex custom CSRs */
+    target_ulong cpuctrlsts;


I mentioned previously, I am not sure if this will be acceptable to upstream (and I'm not actually sure why it's needed, the MIPS and T-Head CSRs don't seem to need to add to the CPUArchState). Either way, it feels like if this is needed, it should be in a separate patch submission to the one adding the alert handler.

agreed, this feels like it shouldn't be here, but I no longer have time to fix this :( we'll see what upstream says

AlexJones0 · 2026-02-19T13:22:19Z

hw/opentitan/meson.build

@@ -0,0 +1,6 @@
+# TomCrypt dependency
+
+libtomcrypt_dep = subproject('libtomcrypt').get_variable('libtomcrypt_dep')


We can't have the tomcrypt dependency for upstream, at least right now.

AlexJones0 · 2026-02-19T13:25:15Z

hw/riscv/ot_earlgrey.c

+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->desc = "RISC-V Board compatible with OpenTitan EarlGrey FPGA platform";


Nit - we probably don't want the "FPGA" references in this commit, but I also don't think that matters much at this stage, especially if it makes rebasing harder.

AlexJones0 · 2026-02-19T13:28:43Z

include/hw/riscv/ibex_common.h

@@ -1,5 +1,5 @@
 /*
- * QEMU RISC-V Helpers for LowRISC Ibex Demo System & OpenTitan EarlGrey
+ * QEMU RISC-V Helpers for LowRISC OpenTitan EarlGrey and related systems


Nit: if possible, it would be good to remove the Ibex demo systems on the original commits rather than the last commit, to reduce confusion when reviewing and polluting the QEMU history.

AlexJones0 · 2026-02-19T13:30:21Z

hw/opentitan/ot_alert.c

@@ -0,0 +1,670 @@
+/*


I suspect upstream will want hw/riscv/opentitan/ or hw/misc/opentitan/ instead but I also think it's fine to leave it as is for now (no need to put a bunch of effort in now if they might be happy with it anyway), especially since you mention this in the initial commit.

yeah, I'm gonna leave it like this and wait for them to complain

Signed-off-by: Lex Bailey <lex.bailey@lowrisc.org>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com> Includes existing MIT licenced code (already published elsewhere)

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

1. Define a generic version of lowrisc-ibex core that can be used in several machines: - leave MISA empty so that generic properties can be defined for this core - remove all arbitrary default properties but ISA I,C,U which are mandatory for ibex - define default mtvec which is only support vectored mode - update privilege version (1.12) according to the Ibex documentation - define ibex architecture identifier - remove hart array (mostly useless, its definition is incoherent and prevent from applying properties to CPU cores) 2. Add an EarlGrey machine that uses this new definition Signed-off-by: Loïc Lefort <loic@rivosinc.com> Signed-off-by: Emmanuel Blot <eblot@rivosinc.com> Signed-off-by: Lex Bailey <lex.bailey@lowrisc.org>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

also adds property no_epmp_cfg on EarlGrey machine to disable default ePMP configuration. Usage: qemu-system-riscv32 -M ot-earlgrey,no-epmp-cfg=true [...] Signed-off-by: Emmanuel Blot <eblot@rivosinc.com> Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com> Includes existing MIT licenced code (already published elsewhere)

Signed-off-by: Lex Bailey <lex.bailey@lowrisc.org> Includes existing MIT licenced code (already published elsewhere)

lexbaileylowrisc and others added 3 commits February 19, 2026 10:47

[ot] target/riscv: rename ibex hart as lowrisc-ibex

4c2365a

Follow vendor-device syntax used with other RISCV cores Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

[ot] hw/char, hw/timer, hw/ssi: fix device definitions

efb4f33

Use a separate Kconfig symbols for Ibex UART, Timer, and SPI devices: having an Ibex CPU does not imply usage of these specific implementations. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

lexbaileylowrisc requested review from AlexJones0, jwnrt and luismarques February 19, 2026 11:02

lexbaileylowrisc mentioned this pull request Feb 19, 2026

(IGNORE THIS ONE) see the other one in the main repo lexbaileylowrisc/qemu#1

Draft

lexbaileylowrisc force-pushed the opentitan-earlgrey branch from b25d9af to 3717ad8 Compare February 19, 2026 11:24

jwnrt reviewed Feb 19, 2026

View reviewed changes

AlexJones0 reviewed Feb 19, 2026

View reviewed changes

lexbaileylowrisc force-pushed the opentitan-earlgrey branch 4 times, most recently from 0ee3636 to 99617b6 Compare February 19, 2026 17:10

rivos-eblot and others added 9 commits February 19, 2026 17:22

[ot] hw/riscv: add helper for Ibex platforms

1992169

Signed-off-by: Lex Bailey <lex.bailey@lowrisc.org>

[ot] target/riscv: implement custom LowRisc Ibex CSRs

5cfa8b2

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com> Includes existing MIT licenced code (already published elsewhere)

[ot] target/riscv: add custom mtvec CSR management

80d15ea

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

[ot] target/riscv: add support for impl-defined initial PMP config

81da2a6

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>

[ot] hw/opentitan: add OpenTitan shadow register helpers

c554eb8

Signed-off-by: Loïc Lefort <loic@rivosinc.com>

[ot] hw/riscv: add an IRQ wrapper

bbbcf08

Signed-off-by: Emmanuel Blot <eblot@rivosinc.com> Includes existing MIT licenced code (already published elsewhere)

[ot] hw/riscv, hw/opentitan: add Opentitan Alert handler device

9ed7dac

Signed-off-by: Lex Bailey <lex.bailey@lowrisc.org> Includes existing MIT licenced code (already published elsewhere)

lexbaileylowrisc force-pushed the opentitan-earlgrey branch from 99617b6 to 9ed7dac Compare February 19, 2026 17:22

		# TomCrypt dependency

		libtomcrypt_dep = subproject('libtomcrypt').get_variable('libtomcrypt_dep')

		* Note: for now, only a minimalist subset of Power Manager device is
		* implemented in order to enable OpenTitan's ROM boot to progress

		@@ -0,0 +1,6 @@
		# TomCrypt dependency

		libtomcrypt_dep = subproject('libtomcrypt').get_variable('libtomcrypt_dep')

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lexbaileylowrisc commented Feb 19, 2026

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