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Certain graph shapes can cause simulation to take exponential time

#1659

· psmears opened

on Mar 18, 2026

Add a diagnostic on `foo: In(1)` being typo'd as `foo: 1`

#1649

· whitequark opened

on Dec 29, 2025

Invalid verilog generated on exhaustive switch statements with assert in default clause

toolchain:yosys

#1648

· qbojj opened

on Dec 29, 2025

Update installation instructions to account for `externally-managed-environment`

#1641

· whitequark opened

on Dec 2, 2025

Tracking issue for RFC 78: Internal I/O ports

#1639

· wanda-phi opened

on Dec 1, 2025

Tighter bounds for integer negation of 1-bit signals

#1631

· CatsAreFluffy opened

on Oct 8, 2025

Pysim performance dependent on module structure

simulator:pysim

#1630

· tilk opened

on Sep 22, 2025

If/Else for combinational assignment generates `always @*` that doesn't initialize

backend:verilog

#1629

· epkRichi opened

on Sep 19, 2025

Memory read port data uninitialized and not resettable

#1625

· epkRichi opened

on Aug 8, 2025

Spaces in names generates invalid `RTLIL`

#1622

· rroohhh opened

on Jul 30, 2025

Tracking issue for RFC 80: Simulation task groups

#1620

· zyp opened

on Jul 28, 2025

Attributes of 2 signals are merged if they're driven by the same source

#1616

· jorolf opened

on Jul 16, 2025