Pinned Loading

1. Adder_SV_testbench Adder_SV_testbench Public

   we have adder, where at posedge of clk, c=a+b; only when valid is enable(i.e = 1) and when rst is high value of a and b and c also rest to zero.

   SystemVerilog

2. APB_single_port_ram_FSM APB_single_port_ram_FSM Public

   🚀 APB-Based Single-Port RAM with FSM-Controlled Read/Write Access 🚀 I recently developed a robust APB-based Single-Port RAM module, incorporating a state machine (FSM) to handle Read and Write tran…

   SystemVerilog 1

3. Async_FIFO_Verification Async_FIFO_Verification Public

   Forked from akzare/Async_FIFO_Verification

   Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.

   SystemVerilog